We describe a procedure for the optimization of a 3C-SiC buffer layer for the deposition of 3C-SiC on (001) Si substrates. A 100 - 150 nm thick SiC buffer was deposited after a standard carbonization at 1125 °C, while increasing the temperature from 1125 °C to 1380 °C.Ramp time influenced the quality and the crystallinity of the buffer layer and the presence of voids at the SiC/Si interface. After the optimization of the buffer, to demonstrate its effectiveness, a high- quality 3C-SiC was grown, with excellent surface morphology, crystallinity and low stress.
HeteroSiC & WASMPE 2013 / Bosi, M., Attolini, G., Negri, M., Frigeri, C., Buffagni, E., Ferrari, C., Rimoldi, T., Cristofolini, L., Aversa, L., Tatti, R., Verucchi, R.. - 806:(2015), pp. 15-19. (HeteroSiC-WASMPE'13 Nizza (F) Giugno 2013) [10.4028/www.scientific.net/MSF.806.15].
HeteroSiC & WASMPE 2013
BOSI, Matteo;NEGRI, Marco;BUFFAGNI, Elisa;RIMOLDI, Tiziano;CRISTOFOLINI, Luigi;
2015-01-01
Abstract
We describe a procedure for the optimization of a 3C-SiC buffer layer for the deposition of 3C-SiC on (001) Si substrates. A 100 - 150 nm thick SiC buffer was deposited after a standard carbonization at 1125 °C, while increasing the temperature from 1125 °C to 1380 °C.Ramp time influenced the quality and the crystallinity of the buffer layer and the presence of voids at the SiC/Si interface. After the optimization of the buffer, to demonstrate its effectiveness, a high- quality 3C-SiC was grown, with excellent surface morphology, crystallinity and low stress.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
