A Resistive SAR A/D Converter for Low-Power Wake-Up Radios

This paper presents a SAR ADC with resistive DAC (RDAC) designed to be integrated in wake-up radio receivers, compliant with the IEEE 802.11ba standard. In the paper, we propose an analysis based on modeling that demonstrates the advantages of using an RDAC over standard solutions with capacitive DAC. The chip was fabricated in 40-nm CMOS technology, and the experimental measurements show good agreement with the simulations of the proposed model. The RDAC SAR ADC exhibits a signal-to-noise and distortion ratio of 33 dB, at 6 bits of nominal resolution. Running at 16 MS/s, the converter shows a Walden FOM of 7.7 fJ/conversion step, one order of magnitude smaller than the SAR ADCs for the same application.