This paper describes a measurement system for mixed-signal accelerators integrating SRAM compute cells. The system is composed of a cascade of blocks, including a MATLAB control software running on a PC, an FPGA to interact with the accelerator circuit, and dedicated peripherals, integrated on the chip. The measurement system supports iterative routines for full memory array and peripheral circuits characterizations. In this paper, we describe the test infrastructure and report the results of the SRAM array characterization.
Test System for an SRAM-Based Mixed-Signal Accelerator / Caselli, Michele; Malena, Francesco; Boni, Andrea. - (2026), pp. 169-175. ( 2025 ApplePies: Applications in Electronics Pervading Industry, Environment and Society Torino ) [10.1007/978-3-032-17174-0_23].
Test System for an SRAM-Based Mixed-Signal Accelerator
Michele Caselli
;Francesco Malena;Andrea Boni
2026-01-01
Abstract
This paper describes a measurement system for mixed-signal accelerators integrating SRAM compute cells. The system is composed of a cascade of blocks, including a MATLAB control software running on a PC, an FPGA to interact with the accelerator circuit, and dedicated peripherals, integrated on the chip. The measurement system supports iterative routines for full memory array and peripheral circuits characterizations. In this paper, we describe the test infrastructure and report the results of the SRAM array characterization.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
