This paper proposes a Matlab framework for the optimized design of Neural Network (NN) mixed-signal accelerators based on the Flipped (F)-2T2R RRAM compute cell. The paper describes an analytical model including the fundamental sources of accelerator non-ideality, developed for a simplified yet accurate system description. The framework allows for an exploration of the design space and optimization of the accelerator for the best system-level performance. Simulations carried out on the model show that the SNR of the system can be maintained with the inclusion of a common-mode compensation circuit in the accelerator architecture. Signal-to-error ratios close to a baseline that considers only the low quantization of the MAC operands as a source of error are obtained for all accelerator sizes. In simulations, mixed-signal accelerators with small dimensions achieve the highest computational efficiency, up to 3000 1b-TOPS/W, but attain a relatively low computational density, limited by the peripheral circuits. On the other hand, large accelerators achieve the maximum computational density, but their computational efficiency is limited to a maximum of 2000 1b-TOPS/W.
An analytical framework for optimized design of mixed-signal accelerators with F-2T2R cells / Caselli, Michele; Boni, Andrea. - In: AEÜ. INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS. - ISSN 1434-8411. - 201:(2025), p. 155970. [10.1016/j.aeue.2025.155970]
An analytical framework for optimized design of mixed-signal accelerators with F-2T2R cells
Caselli, Michele;Boni, Andrea
2025-01-01
Abstract
This paper proposes a Matlab framework for the optimized design of Neural Network (NN) mixed-signal accelerators based on the Flipped (F)-2T2R RRAM compute cell. The paper describes an analytical model including the fundamental sources of accelerator non-ideality, developed for a simplified yet accurate system description. The framework allows for an exploration of the design space and optimization of the accelerator for the best system-level performance. Simulations carried out on the model show that the SNR of the system can be maintained with the inclusion of a common-mode compensation circuit in the accelerator architecture. Signal-to-error ratios close to a baseline that considers only the low quantization of the MAC operands as a source of error are obtained for all accelerator sizes. In simulations, mixed-signal accelerators with small dimensions achieve the highest computational efficiency, up to 3000 1b-TOPS/W, but attain a relatively low computational density, limited by the peripheral circuits. On the other hand, large accelerators achieve the maximum computational density, but their computational efficiency is limited to a maximum of 2000 1b-TOPS/W.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.


