This paper presents a 2048 bit, rate (1)/(2) soft decision decoder for a new class of codes known as Turbo Gallager Codes. The decoder can support tip to 1 Gbit/s code rate and performs up to 48 decoding iteration ensuring at the same time high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 mum standard-cell CMOS technology.

A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 turbo Gallager code decoder / Ciao, P; Colavolpe, G; Fanucci, L. - (2004), pp. 174-181. (Intervento presentato al convegno EUROMICRO Symp. on Digital System Design, Architectures, Methods and Tools tenutosi a Rennes, France nel August-September 2004).

A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 turbo Gallager code decoder

Colavolpe, G;
2004-01-01

Abstract

This paper presents a 2048 bit, rate (1)/(2) soft decision decoder for a new class of codes known as Turbo Gallager Codes. The decoder can support tip to 1 Gbit/s code rate and performs up to 48 decoding iteration ensuring at the same time high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 mum standard-cell CMOS technology.
2004
A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 turbo Gallager code decoder / Ciao, P; Colavolpe, G; Fanucci, L. - (2004), pp. 174-181. (Intervento presentato al convegno EUROMICRO Symp. on Digital System Design, Architectures, Methods and Tools tenutosi a Rennes, France nel August-September 2004).
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11381/2964301
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