This paper presents a 2048 bit, rate (1)/(2) soft decision decoder for a new class of codes known as Turbo Gallager Codes. The decoder can support tip to 1 Gbit/s code rate and performs up to 48 decoding iteration ensuring at the same time high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 mum standard-cell CMOS technology.
A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 turbo Gallager code decoder / Ciao, P; Colavolpe, G; Fanucci, L. - (2004), pp. 174-181. ( EUROMICRO Symp. on Digital System Design, Architectures, Methods and Tools Rennes, France August-September 2004).
A parallel VLSI architecture for 1-Gb/s, 2048-b, rate-1/2 turbo Gallager code decoder
Colavolpe, G;
2004-01-01
Abstract
This paper presents a 2048 bit, rate (1)/(2) soft decision decoder for a new class of codes known as Turbo Gallager Codes. The decoder can support tip to 1 Gbit/s code rate and performs up to 48 decoding iteration ensuring at the same time high throughput and good coding gain. In order to evaluate the performance and the gate complexity of the decoder VLSI architecture, it has been synthesized in a 0.18 mum standard-cell CMOS technology.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
