This paper proposes the design of a Pulse Width Modulation Digital to Analog Converter (PWM-DAC) for Analog in-Memory Computing. The converter generates voltage pulses, with pulse-width proportional to the 7-bit digital input, in sign-magnitude format. The circuit is designed in a 22-nm FD-SOI technology, with a layout tailored for the severe pitch and area requirements of the memory array for AiMC. The circuit achieves sub-500 fJ/conversion energy consumption, supplied at 0.85 V. The converter obtains an Integral-Non-Linearity (INL) and Differential-Non-Linearity (DNL), normalized at the LSB, lower than 7% and 12%, respectively.

A PWM-DAC for Analog In-Memory Computing in Mixed-Signal Accelerators / Malena, Francesco; Boni, Andrea; Caselli, Michele. - (2023), pp. 273-276. (Intervento presentato al convegno PRIME tenutosi a Valencia) [10.1109/PRIME58259.2023.10161781].

A PWM-DAC for Analog In-Memory Computing in Mixed-Signal Accelerators

Malena, Francesco;Boni, Andrea;Caselli, Michele
2023-01-01

Abstract

This paper proposes the design of a Pulse Width Modulation Digital to Analog Converter (PWM-DAC) for Analog in-Memory Computing. The converter generates voltage pulses, with pulse-width proportional to the 7-bit digital input, in sign-magnitude format. The circuit is designed in a 22-nm FD-SOI technology, with a layout tailored for the severe pitch and area requirements of the memory array for AiMC. The circuit achieves sub-500 fJ/conversion energy consumption, supplied at 0.85 V. The converter obtains an Integral-Non-Linearity (INL) and Differential-Non-Linearity (DNL), normalized at the LSB, lower than 7% and 12%, respectively.
2023
979-8-3503-0320-9
A PWM-DAC for Analog In-Memory Computing in Mixed-Signal Accelerators / Malena, Francesco; Boni, Andrea; Caselli, Michele. - (2023), pp. 273-276. (Intervento presentato al convegno PRIME tenutosi a Valencia) [10.1109/PRIME58259.2023.10161781].
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11381/2952892
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