Abstract—This paper presents a novel architecture of a self- calibrating programmable voltage reference with nanoampere current consumption. The output voltage is generated by a programmable impedance matrix, based on MOS transistors and resistors, and periodically calibrated with a duty-cycled bandgap. In application domains where the temperature exhibits a low rate-of-change, an average current consumption of 6.5 nA is achieved, largely outperforming all the previously reported switched-capacitor or floating-gate architectures. Implemented in 55-nm CMOS technology, the reference exhibits a 0.4-to-2.5-V output voltage range, over the -20 to +80◦ C temperature range.
A 6.5 nA Static Self-Calibrating Programmable Voltage Reference for Smart Socs / Caselli, Michele; Tiurin, Evgenii; Stanzione, Stefano; Boni, Andrea. - (2021). (Intervento presentato al convegno 28th IEEE International Conference on Electronics Circuits and Systems tenutosi a Dubai nel 28 Novembre - 1 Dicembre) [10.1109/ICECS53924.2021.9665463].
A 6.5 nA Static Self-Calibrating Programmable Voltage Reference for Smart Socs
Michele Caselli;Andrea Boni
2021-01-01
Abstract
Abstract—This paper presents a novel architecture of a self- calibrating programmable voltage reference with nanoampere current consumption. The output voltage is generated by a programmable impedance matrix, based on MOS transistors and resistors, and periodically calibrated with a duty-cycled bandgap. In application domains where the temperature exhibits a low rate-of-change, an average current consumption of 6.5 nA is achieved, largely outperforming all the previously reported switched-capacitor or floating-gate architectures. Implemented in 55-nm CMOS technology, the reference exhibits a 0.4-to-2.5-V output voltage range, over the -20 to +80◦ C temperature range.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
