The paper describes the design of a pipelined analog-to-digital converter (ADC), featuring 14 bit resolution and 100 MS/s conversion speed, with 2 Vppinput range and 3.3 V power supply. The targetwas an INL/DNL error within 0.5 LSB of INL/DNL, with a low power consumption. The optimization of the converter architecture, i.e. the partitioning of the ADC's resolution among the stages of the pipeline chain, was carried out by means of a behavioral model. A single-stage telescopic OTA providing a large GBWproduct at a moderate power consumption was used in the first stages. Capacitor shuffling calibration was introduced in order to eliminate the effects of the capacitors mismatch on the converter THD. The chip was implemented in a 0.18μm CMOS technology. The power dissipation is 150 mW and the simulated SFDR is 84 dB.
Design of a 14-bit, 100-MS/S, pipelined analog-to-digit al convertor in 0.18-μm cmos technology / Vecchi, D.; Azzolini, C.; Boni, A.; Chaahoub, F.; Crespi, L.. - 2005:510(2005). (Intervento presentato al convegno 5th IEE International Conference on Advanced A/D and D/A Conversion Techniques and Their Applications, ADDA 2005 tenutosi a irl nel 2005).
Design of a 14-bit, 100-MS/S, pipelined analog-to-digit al convertor in 0.18-μm cmos technology
Vecchi D.;Azzolini C.;Boni A.;Crespi L.
2005-01-01
Abstract
The paper describes the design of a pipelined analog-to-digital converter (ADC), featuring 14 bit resolution and 100 MS/s conversion speed, with 2 Vppinput range and 3.3 V power supply. The targetwas an INL/DNL error within 0.5 LSB of INL/DNL, with a low power consumption. The optimization of the converter architecture, i.e. the partitioning of the ADC's resolution among the stages of the pipeline chain, was carried out by means of a behavioral model. A single-stage telescopic OTA providing a large GBWproduct at a moderate power consumption was used in the first stages. Capacitor shuffling calibration was introduced in order to eliminate the effects of the capacitors mismatch on the converter THD. The chip was implemented in a 0.18μm CMOS technology. The power dissipation is 150 mW and the simulated SFDR is 84 dB.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
