Two novel BiCMOS latched comparators operating at 3.3V with 8bit resolution are presented. They achieve approx.200MHz operation and exhibit lower power consumption than the conventional architecture. The first resembles a conventional bipolar latched comparator, with a variable load resistance which changes its value three times during the acquisition cycle. It achieves the highest speed and the lowest power consumption. The second includes a differential amplifier which unbalances a ground-referenced latch by current mirror action. It may be adapted to even lower supply voltages and exhibits negligible kick-back effects.
|Titolo:||Low-power, low-voltage BiCMOS comparators for approx.200MHz, 8bit operation|
|Data di pubblicazione:||1996|
|Appare nelle tipologie:||4.1b Atto convegno Volume|