The design of an FPGA hardware architecture requires, traditionally, its description in a dedicated language (Hardware Description Language, HDL), which is often not well suited to manage wide and complex models. The design process can be simplified if the entire architecture can be described in a high abstraction level framework such as Simulink. In this paper a Simulink model-based design of a pipelined accumulator suitable for applications such as Support Vector Machine algorithms is presented. The compatibility with the HDL Coder workflow enables the direct FPGA model implementation. Moreover, the workflow output has been compared with a native VHDL equivalent floating-point accumulator intellectual property.
|Titolo:||A Simulink Model-Based Design of a Floating-Point Pipelined Accumulator with HDL Coder Compatibility for FPGA Implementation|
|Data di pubblicazione:||2020|
|Appare nelle tipologie:||2.1 Contributo in volume(Capitolo di libro)|