Multiplication is a fundamental operation in most signal and image processing applications. In this paper, a new architecture for a Vedic multiplier implementing ‘Urdhava-tiryakbhyam’ methodology is proposed. The presented architecture is completely modular and is conceived to be implemented in model-based designs where the configurability is of utmost importance. This architecture is prone to be implemented both as pure combinational and pipelined fashion to fit the needed frequency clock. The proposed multiplier exploits 4:2 compressor blocks instead of standard full-adders. Five different 4:2 compressor architectures from literature have been compared. The designs are developed as model-based schemes in SIMULINK and then automatically coded in VHDL (Very High-speed Integrated Circuits Hardware Description Language) through the HDL coder of MATLAB. The code is synthetized on an Artix 7 FPGA (Field Programmable Gate Array) and performances are evaluated in terms of area occupancy (i.e., LUTs number) and propagation delay (i.e., output time). Results show that despite the achieved configurability and modular architecture, the proposed solution performs equally or in some cases even better compared to solutions already presented in literature.

A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms / Bianchi, V.; De Munari, I.. - In: MICROPROCESSORS AND MICROSYSTEMS. - ISSN 0141-9331. - 76(2020), p. 103106. [10.1016/j.micpro.2020.103106]

A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms

Bianchi V.;De Munari I.
2020

Abstract

Multiplication is a fundamental operation in most signal and image processing applications. In this paper, a new architecture for a Vedic multiplier implementing ‘Urdhava-tiryakbhyam’ methodology is proposed. The presented architecture is completely modular and is conceived to be implemented in model-based designs where the configurability is of utmost importance. This architecture is prone to be implemented both as pure combinational and pipelined fashion to fit the needed frequency clock. The proposed multiplier exploits 4:2 compressor blocks instead of standard full-adders. Five different 4:2 compressor architectures from literature have been compared. The designs are developed as model-based schemes in SIMULINK and then automatically coded in VHDL (Very High-speed Integrated Circuits Hardware Description Language) through the HDL coder of MATLAB. The code is synthetized on an Artix 7 FPGA (Field Programmable Gate Array) and performances are evaluated in terms of area occupancy (i.e., LUTs number) and propagation delay (i.e., output time). Results show that despite the achieved configurability and modular architecture, the proposed solution performs equally or in some cases even better compared to solutions already presented in literature.
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11381/2876145
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 14
  • ???jsp.display-item.citation.isi??? 2
social impact