Radio-Frequency (RF) energy harvesting must cope with the limited availability and high variability of the energy source. In this paper, the modeling of an RF harvester for ultra low power environments is presented. A mathematical model based on theoretical analysis is developed. The model demonstrates that the maximum transferred power point is located in a three-dimensional space defined by the input capacitance, the output voltage, and the load resistance of the rectifier circuit. Moreover, the mathematical model returns results in substantial agreement with the SPICE simulation results, while guaranteeing a remarkable reduction of the required computation time. Furthemore, the paper reports the implementation of a mixed signal system for the 3-D MPPT, to be embedded in an RF harvester, in a 65 nm CMOS technology. The circuit exhibits a simulated power consumption lower than 100 nW, making this solution suitable for ultra low power harvesting.
Modeling and design of 3-D MPPT for ultra low power RF energy harvesters / Caselli, Michele; Boni, Andrea. - In: INTEGRATION. - ISSN 0167-9260. - (2020). [10.1016/j.vlsi.2020.02.008]
Modeling and design of 3-D MPPT for ultra low power RF energy harvesters
Michele Caselli;Andrea Boni
2020-01-01
Abstract
Radio-Frequency (RF) energy harvesting must cope with the limited availability and high variability of the energy source. In this paper, the modeling of an RF harvester for ultra low power environments is presented. A mathematical model based on theoretical analysis is developed. The model demonstrates that the maximum transferred power point is located in a three-dimensional space defined by the input capacitance, the output voltage, and the load resistance of the rectifier circuit. Moreover, the mathematical model returns results in substantial agreement with the SPICE simulation results, while guaranteeing a remarkable reduction of the required computation time. Furthemore, the paper reports the implementation of a mixed signal system for the 3-D MPPT, to be embedded in an RF harvester, in a 65 nm CMOS technology. The circuit exhibits a simulated power consumption lower than 100 nW, making this solution suitable for ultra low power harvesting.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.