The brief presents the design and the implementation of a very-high speed track-and-hold amplifier (THA) for analog-digital converters with high input bandwidth. The THA is based on a half-bridge driving a switched-emitter follower. A lower power consumtpion and a simpler circuit architecture than previously reported bipolar implementations were achieved by means of circuit optimization. In particular, the impact of the aspect ratio of the pMOS current generator in the bridge on the harmonic distortion and on the hold-mode behavior is discussed and modeled. Furthermore, a modification of the cancellation capacitor for feedthrough attenuation, fully compatible with the latest BiCMOS technologies is proposed. The THA was implemented in a 0.8-μm SiGe BiSMOS with 30-GHz fT. It features 10-b resolution at a sampling frequency of 1-GS/s at Nyquist with less than 25 mW of power consumption, from a single 2.7-V power supply.
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