In this paper, the isothermal wafer-level electromigration test method has been used to compare the resistance to electromigration damage of multi-level structures, realized by dual-damascene copper technology with a variable number of vias. ‘‘Upstream’’ and ‘‘downstream’’ structures have been defined, depending on the metal level where the line under test was located, with respect to the metal level where current and voltage taps were drawn. Not unexpectedly, the most critical current path for electromigration has been found in downstream structures, where the electron flow is entering the line under test. Worthy of note, a well defined dependence of the time to failure on the number of vias has been observed for these structures. Activation energy and current-density acceleration coefficient have been extracted and a quantitative relation is proposed to relate the lifetime expectancy to the number of vias.
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