The paper discusses the design of a very highspeed 8-b analog-to-digital converter (ADC) in 0.18-/spl mu/m CMOS. A conversion rate as high as 2GS/s with a relatively low power consumption was achieved by means of a couple of interleaved subranging/flash ADC with a single track-and-hold at the input. Special design solutions were adopted for implementing subranging operation at such a high frequency. Finally, a lower power consumption self-calibrating technique effective for reducing nonlinearity errors below 1 LSB was implemented.
Design of a 2-GS/s 8-b Self-Calibrating ADC in 0.18-um CMOS Technology / Azzolini, Cristiano; Boni, Andrea; Facen, A.; Parenti, M.; Vecchi, D.. - (2005), pp. 1386-1389. (Intervento presentato al convegno ISCAS 2005 tenutosi a Kobe, Giappone nel Maggio 2005) [10.1109/ISCAS.2005.1464855].
Design of a 2-GS/s 8-b Self-Calibrating ADC in 0.18-um CMOS Technology
AZZOLINI, Cristiano;BONI, Andrea;A. FACEN;M. PARENTI;D. VECCHI
2005-01-01
Abstract
The paper discusses the design of a very highspeed 8-b analog-to-digital converter (ADC) in 0.18-/spl mu/m CMOS. A conversion rate as high as 2GS/s with a relatively low power consumption was achieved by means of a couple of interleaved subranging/flash ADC with a single track-and-hold at the input. Special design solutions were adopted for implementing subranging operation at such a high frequency. Finally, a lower power consumption self-calibrating technique effective for reducing nonlinearity errors below 1 LSB was implemented.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
