Ultra-thin gate dielectrics are exploited in fabrication of MOSFET's featuring channel lengths in the decananometer range: the ITRS indicates that oxide thickness in the order of 1 nm will be used in 2005 for ultra-short CMOS. For such aggressively scaled devices, gate-leakage currents represent a critical issue. In this paper, a study on the impact of Direct-Tunneling (DT) current on the behaviour of a wide variety of CMOS circuits is presented, based on a simulation strategy aimed at predicting the correlation of major performance indices with oxide thickness.
Impact of Gate-leakage Currents on CMOS Circuit Performance / Marras, A.; DE MUNARI, Ilaria; Vescovi, D.; Ciampolini, Paolo. - STAMPA. - 24:2(2004), pp. 653-656. (Intervento presentato al convegno 24th International Conference on Microelectronics (MIEL 2004) tenutosi a Nis, Serbia nel 16-19 May 2004) [10.1109/ICMEL.2004.1314913].
Impact of Gate-leakage Currents on CMOS Circuit Performance
DE MUNARI, Ilaria;CIAMPOLINI, Paolo
2004-01-01
Abstract
Ultra-thin gate dielectrics are exploited in fabrication of MOSFET's featuring channel lengths in the decananometer range: the ITRS indicates that oxide thickness in the order of 1 nm will be used in 2005 for ultra-short CMOS. For such aggressively scaled devices, gate-leakage currents represent a critical issue. In this paper, a study on the impact of Direct-Tunneling (DT) current on the behaviour of a wide variety of CMOS circuits is presented, based on a simulation strategy aimed at predicting the correlation of major performance indices with oxide thickness.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
