Ultra-thin gate dielectrics are exploited in fabrication of MOSFETs featuring channel lengths in the decananometer range: according to the ITRS oxide thickness in the order of 1nm will be used in 2005 for ultra-short channel CMOS. For such aggressively scaled devices, gate-leakage currents represent a critical issue. In this paper, a study on the impact of direct-tunneling (DT) current on the performance of a wide variety of CMOS circuits is presented. The approach relies on a mixed-mode simulation approach, which allows for predicting the correlation of major performance indices with oxide thickness.
Impact of gate-leakage currents on CMOS circuit performance / Marras, Alessandro; DE MUNARI, Ilaria; D., Vescovi; Ciampolini, Paolo. - In: MICROELECTRONICS RELIABILITY. - ISSN 0026-2714. - 45, No. 3-4:(2005), pp. 499-506. [10.1016/j.microrel.2004.09.006]
Impact of gate-leakage currents on CMOS circuit performance
MARRAS, Alessandro;DE MUNARI, Ilaria;CIAMPOLINI, Paolo
2005-01-01
Abstract
Ultra-thin gate dielectrics are exploited in fabrication of MOSFETs featuring channel lengths in the decananometer range: according to the ITRS oxide thickness in the order of 1nm will be used in 2005 for ultra-short channel CMOS. For such aggressively scaled devices, gate-leakage currents represent a critical issue. In this paper, a study on the impact of direct-tunneling (DT) current on the performance of a wide variety of CMOS circuits is presented. The approach relies on a mixed-mode simulation approach, which allows for predicting the correlation of major performance indices with oxide thickness.| File | Dimensione | Formato | |
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