Performance Evaluation of Ultra Thin gate Oxide CMOS Circuits

Gate currents are becoming a major concern for ULSI circuit designers. A standard circuit design flow that takes into account such effects is needed in order to take advantage from nanometer-sized devices performance. Some suggestions on how to approach permeable-gate-device circuit simulation are proposed in this paper, focusing on gate current-related effects on circuit performance. A simple, yet complete, standard CMOS circuit has been designed and its functional and performance indices have been evaluated, depending on the actual oxide thickness. To correlate performance directly to the fabrication parameters, a mixed-mode approach using both physical and circuit simulations has been adopted. Model parameters were calibrated on actual measurements. Simulation results have been compared for ideal- and permeable-gate devices. Although circuit functionality is not affected (within the considered technology range, at least), significant performance alterations are highlighted.