Low-Power Circuits in CMOS Technology for Smart and Portable IoT Devices

This thesis addresses the challenges faced by Internet of Things (IoT) and Artificial Intelligence of Things (AIoT) devices, specifically the need for energy-efficient solutions that support AI capabilities at the edge while preserving battery lifetimes. The work focuses on two primary areas: integrating smart computing capabilities at the edge and designing a low-power multiple-output voltage reference for power management. A novel solution is proposed for executing deep neural networks efficiently by implementing the Analog in-Memory Computing (AiMC) paradigm. A mixed-signal accelerator is presented, focusing on the design of the Single-Pulse-Delay-Chain (SPDC) Digital-to-Analog Converter (DAC). The circuit achieves high linearity and low energy consumption, with a narrow layout pitch, which is essential in dense accelerator macro. Additionally, the thesis presents the CuReus-VREF, a low-power, multiple-output voltage reference that generates stable voltages with nano amperes current consumption, suitable for power-constrained systems such as implantable devices. By limiting the energy requirements, the proposed solutions aim to facilitate the use of energy harvesters and address environmental concerns related to battery disposal. The main contributions lie in the design of a new DAC for mixed-signal accelerators in the AiMC context, and an ultra-low-power voltage reference, offering scalable, energy-efficient solutions for IoT and AIoT devices.